In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily, or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is the preferred electrical isolation technique especially for a semiconductor chip with high integration. In general, conventional methods of producing an STI feature include forming a hard mask over the trench layer, patterning a photoresist etching mask over the hard mask, etching the hard mask through the photoresist etching mask to form a patterned hard mask, and thereafter etching the trench layer to form the STI feature. Subsequently, the photoresist etching mask is removed and the STI feature is back-filled with a dielectric material.
Frequently STI features are etched in a sequential process flow, where the mask layers are etched in one chamber and the silicon trench is etched in another chamber. Dry etching is performed by way of a plasma, or reactive ion etch (RIE). Typically, in a plasma etching process, an etchant source gas is supplied to an etching chamber where the plasma is ignited to generate ions from the etchant source gas. Ions are then accelerated towards the process wafer surface, frequently by a voltage bias, where they impact and remove material (etch) from the process wafer. Various gas chemistries are used to provide variable etching rates for different etching target materials. Frequently used dry etchant source gases include chloro and fluoro-hydrocarbons in addition to chlorine (Cl2) and HBr to etch through a metal nitride layer, for example silicon nitride (SiN), followed by etching through a silicon layer to form, for example, a shallow trench isolation (STI) feature.
One chemistry for etching through silicon, for example, includes a Cl2/O2/HBr-based chemistry. During and after the etching process halogen species such as chlorine and bromine which are highly hydrophilic remain on the process wafer target surface where, for example, they are incorporated into the sidewalls and bottoms of etched features as well as into overlying layers of photoresist. Since water is also present in and around the process wafer target surface, corrosive condensates including, for example, HBr and HCl may form on the process wafer surface causing corrosive damage to etched features, especially the edges and corners. HBr, for instance, is a highly corrosive acid that is frequently formed on the surface of the process wafer, especially at etched feature edges where the higher surface tension facilitates condensation.
FIG. 1A shows a schematic representation of typical process chamber configuration used in STI etching. The typical STI etching apparatus, for example, includes several different ambient controlled etching chambers, 10, 12, 14, and 16, in addition to a wafer orientation chamber 18, a cool down chamber 24 and loadlock chambers 20 and 22, all ambient controlled. The robotic arm transfer mechanism 26 is centrally located in central ambient controlled transfer chamber 28. In a typical process in STI etching, as explained, several different etching steps with different etching chemistries may be involved thus necessitating transfer of the process wafer by robotic arm 26 between multiple etching chambers, for example 10, 12, 14, and 16. Following etching, the process wafer may be transferred through transfer chamber 28 by robotic arm 26 to cool down chamber 24 to cool the process wafer prior to transfer to loadlock chamber, for example, 20 or 22 where the chamber is pressurized to atmospheric pressure for unloading the process wafer.
For example, referring to FIG. 1B process flow diagram, in operation, according to the prior art, in an STI process, a process wafer (not shown) is loaded according to process 102 into loadlock chamber e.g., 20 where robotic arm 26 transfers the wafer to wafer orientation chamber 18 under controlled ambient conditions through transfer space 28 for wafer orientation process 104 followed by process step 106 where the process wafer is transferred to e.g., chamber 10 for dry etching through an upper layer of silicon nitride on the process wafer surface defined by an overlying layer of photoresist, the dry etching chemistry, for example, including HBr and Cl2. Following process 106, the process wafer is transferred to e.g., chamber 14 where process 108 including dry etching through an underlying silicon layer to form the trench for the STI is carried out, chamber 34 being optimized for carrying out the dry etching process. Following trench forming dry etching process 108, the process wafer is typically transferred via robotic arm 26 to ashing chamber, e.g., 12 where the photoresist is at least partially removed according to an oxygen plasma ashing process 110. Following process 110, the process wafer is typically transferred to chamber, e.g., 24, for cooling down process 112 prior to transfer to loadlock chamber e.g., 22 for unloading process 114. Following the unloading process, the wafer is typically subjected to another ex-situ wet etching process 116 followed by ex-situ cleaning process 118 to remove residual contamination, including HBr and HCl, remaining on the process wafer surface.
During the dry etching processes to form the STI feature, corrosive volatile residues including, for example, HBr and HCl may condense onto the process wafer surface which may also have residual particles adhering to the surface from the etching process. Further, during the pressurization process in the loadlock chamber to remove the process wafer, the residual particles including corrosive condensates may become dislodged and adhere to the chamber walls and robotic arm thereby causing corrosive damage to the chamber and associated chamber parts. As a result, over time, the loadlock chamber accumulates residual corrosive particles which can contaminate process wafers causing corrosive damage as they are moved through the loadlock chamber thereby necessitating frequent equipment shutdown for cleaning. Another shortcoming of the prior art procedure and apparatus for STI etching, and etching in general, may be potential adverse health consequences to equipment operators from an undesired buildup of such contamination and associated vapors present within the chamber and upon the process wafer upon unloading the process wafer. HBr fumes, for example, are known to be highly dangerous and costly safety procedures are made necessary by the residual HBr contamination on the process wafer.
The practice in the prior art, for removing residual contaminants, for example, HBr or HCl, utilizes an ex-situ cleaning procedure where the process wafer is either heated or exposed to ultraviolet light to volatize (vaporize) the residual contamination. In addition, costly automated optical imaging systems to spot defects caused by the corrosive residual contamination are made necessary to ensure quality control.
There is therefore a need in the semiconductor processing art to develop methods whereby the level of residual contaminants remaining on semiconductor process wafers following dry etching is reduced thereby minimizing damage to both the process wafer and etching apparatus as well as reducing the danger of adverse health consequences to manufacturing personnel.
It is therefore an object of the invention to provide a method whereby the level of residual contamination remaining on semiconductor process wafers following a dry etching process is reduced thereby minimizing damage to both the process wafer and etching apparatus as well as reducing the danger of adverse health consequences to manufacturing personnel while overcoming other shortcomings and deficiencies in the prior art.